In the manufacture of semiconductor devices, especially on advanced nodes, most of the Back End Of Line (BEOL) layers need to be patterned by multiple lithographic exposure (L) and etch (E) sequences due to limitations in lithographic printability at dense pitch. For this reason, forming connection lines of well-defined length becomes very challenging. A typical sequence for the formation of such connection lines starts by forming trenches in a hard mask (in multiple LE sequences), followed by defining interruptions to those trenches. At dense pitch also these interruptions do require multiple LE sequences. A major issue with this method is that the number of layers in the hard mask stack increases with the number of layers required to define the blocked portions. If more than one lithographic mask must be used, the number of layers in the hard mask stack quickly becomes unpractical. The challenge is now to enable the patterning of these interruptions, even when more than one lithographic mask must be used, without having to increase the number of layers in the hard mask stack in line with the number of layers required to define the trench interruptions.